The Elimination of Stacking Faults by Preoxidation Gettering of Silicon Wafers: III . Defect Etch Pit Correlation with p‐n Junction Leakage

Abstract

Recently described procedures for the elimination of oxidation‐induced stacking faults have been incorporated into a device processing line to yield data on the leakage in p‐n junction tester diodes. The gettering processes, which take place on the back side of a wafer before the first oxidation, include the deliberate introduction of misfit dislocations and/or the deposition of a highly strained layer of . The results show that leakage currents can be reduced by several orders of magnitude and diode yields increased from about 10% to greater than 90%. By doing “post mortem” chemical etch pit studies on previously electrically mapped arrays of diodes the relative effectiveness of the two gettering schemes are compared. Factors such as the type of stacking fault, whether it be related to a native or process‐induced source, or whether it is clean or decorated are discussed as well as the influence of slip‐type dislocations.