A Model for Threshold Voltage Shift under Positive and Negative High-Field Electron Injection in Complementary Metal-Oxide-Semiconductor (CMOS) Transistors

Abstract

High-field electron injection is an attractive tool for investigation of properties of thin dielectric layers. The paper discusses the threshold voltage degradation of complementary metal-oxide-semiconductor (CMOS) devices due to high field oxide stressing. Both the filling of existing oxide hole and electron traps and the generation of new defects, namely bulk electron traps and interface states, are carefully considered. It is shown that monitoring of stress voltage transients during constant-current electron injection into the device gate oxide may be very helpful in understanding degradation phenomena. A qualitative model is proposed to explain different behavior and susceptibility of the threshold voltage of CMOS devices to F-N stress-induced degradation. The model is based on differences in charge trapping and detrapping in different regions of very thin gate oxides under different stress conditions in p-type MOS (PMOS) and n-type MOS (NMOS) transistors.