A 65,664 bit, 4 μm, minor loop chip of 128 loops of 513 bits is described. The goals of fast read and write access, and high average data rates are shown to lead to a decision to use a replicate switch of compact design to minimize loop length and data housekeeping. Operation of the device is described, followed by an example of a read and write of a single block of data and examples of read/write of multiple blocks. Use of modulo 128 and modulo 151 block address assignments illustrate means of obtaining either gapless and gapped record delivery.