A 1K-gate GaAs gate array

1 January 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVII, 40-41
https://doi.org/10.1109/isscc.1984.1156640

Abstract

A 1050-gate GaAs gate array connected as a 6 × 6b parallel multiplier, which exhibits a multiplication time of 10.6ns and 350mW power dissipation, will be covered.

Keywords

GALLIUM ARSENIDE
LOGIC ARRAYS
INTEGRATED CIRCUIT INTERCONNECTIONS
INVERTERS
RESEARCH AND DEVELOPMENT
FETS
INTEGRATED CIRCUIT TECHNOLOGY
DELAY EFFECTS
LOGIC DESIGN

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