Avalanche punch-through erase (APTE) mode in dual-dielectric charge-storage (DDC) cells

Abstract

The erase of multilayer charge-storage memory cells by a reverse-bias pulsing of source and drain with the gate and substrate grounded has been previously suggested. Here the physical mechanisms behind this erase mode are explored. It is shown that both punch-through and avalanche are necessary for its operation. This avalanche punch-through erase (APTE) succeeds by pumping majority carriers into a potential pocket at the interface, thereby raising the interface surface potential to a level high enough to allow the stored charge to tunnel out. It is found experimentally that APTE is strongly affected by the lateral leakage of carriers from the pocket. Theoretical curves are presented which show how the pocket itself is affected by the cell geometry, doping level, and pulse amplitude. It appears that APTE is particularly suitable for reprogrammable read-often memories (REPROM's) using dual-dielectric memory cells (DDC/s) with interfacial dopant. These cells allow the use of a gate inhibit voltage pulse which is shown to increase the effectiveness of the APTE, making it a practical approach for random-access REPROM integrated circuits.