GaAs digital IC technology/statistical analysis of device performance

Abstract

A new approach to the design and fabrication of GaAs digital integrated circuits capable of high speed and low power dissipation has been demonstrated. This technology relies on Schottky-diode FET logic (SDFL) circuits which take advantage of the high switching speed of Schottky diodes and the high transconductance of the GaAs 1-µm gate MESFET. These circuits are fabricated by localized implantations directly into the semi-insulating GaAs substrate. Excellent results in terms of speed and power dissipation have been achieved, while circuit complexity has lrapidly grown as demonstrated by the successful operation of an eight-channel multiplexer, an eight-channel demultiplexer, and a 3 × 3 parallel multiplier employing 64, 60, and 75 gates, respectively. This rapid progress requires considerable work in monitoring the process through statistical evaluation of test devices. This paper discusses the process monitoring work carried out in support of the technology, The organization of the masks used for circuit development is described, with emphasis on process monitoring test patterns. Automatic instrumentation used to gather a large amount of statistical information is described, and wafer maps illustrating statistical results are presented and discussed. Uniformity of device characteristics over the full wafer and over smaller areas (circuit size) is compared. Implications of these results are discussed in terms of circuit yield.