On driving many long lines in a VLSI layout

Abstract

We assume that long wires represent large capacitive loads, and investigate the effect on the area of a VLSI layout when drivers are introduced along many long wires in the layout. We present a layout for which the introduction of drivers along long wires squares the area of the layout; we show, however, that the increase in area is never greater than this, if the driver can be laid out in a square region. We also show an area-time trade-off for a single long wire by which we can reduce the area of its driver to Θ(lq), q ≪ 1, from Θ(l), if we can tolerate a delay of Θ(l1-q) rather than Θ(log l); and we obtain tight bounds on the worst-case area increase in general lay-outs having these drivers, using the Brouwer fixed-point theorem. We also derive results for the case when drivers are embedded in rectangles that are not square. Finally, we extend the use of our upper-bound technique to other layout, problems.