Computer Reduction of Two-Level, Multiple-Output Switching Circuits

1 January 1969

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-18 (1), 58-63
https://doi.org/10.1109/t-c.1969.222525

Abstract

An algorithm which reduces the number of gates and connections (diodes) in two-level, multiple-output combinational logic networks is presented and compared with conventional minimization procedures.

Keywords

CIRCUITS
LOGIC
DIODES
PROCEDURES
MINIMIZATION
GATES
MULTIPLE OUTPUT SWITCHING
REDUCTION OF TWO

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