A FASTBUS Processor Interface Using a 68000 Microprocessor
- 1 January 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 31 (1), 188-192
- https://doi.org/10.1109/tns.1984.4333242
Abstract
A versatile FASTBUS master utilize a 68000 microprocessor has been developed. The module implements geographical, logical and broadcast addressing and is able to handle the FASTBUS Service Request. The data transfer rate is about 800 kB/sec by using window driver. The logics and test results are described.Keywords
This publication has 1 reference indexed in Scilit:
- A Status Report of FASTBUS at KEKIEEE Transactions on Nuclear Science, 1983