In this paper trends in CAD for application specific IC's (ASIC) are discussed. Shortage of skilled silicon designers, too long time to market and too low level of design as in standard cells and gate arrays, lead to a design strategy whereby system design is strictly separated from silicon design. (Meet-in-the-middle design). System designers will use interactive, knowledge based synthesis tools adressing a number of well defined target architectures to be generated from a formal specification language. Architectures are defined as a connection of a well defined set of reusable and parameterizable modules which are predesigned by silicon specialists. This is no longer done on a CALMA type environment but on an interpretative symbolic programming environment. This environment supports automatic parameterization and generation of layout, timing and testing views as well as automatic adaptability to new technology rules. Verification will be shifting away from costly simulation to knowledge based verification, based on a formal definition of design styles and automatic theorem proving. This will require multiprocessor workstations unifying high speed graphics and imperative, declarative and symbolic programming styles. A major problem with this methodology will be the (re)education of design engineers in order to design hardware the « soft» way