A High Density Programmable Logic Array Chip

Abstract

A programmable logic array (PLA) chip design using special array folding techniques and an on-chip bus structure has been developed. It overcomes the sparseness in conventional large PLA configurations. The design is a masterslice FET chip personalized for the particular application during processing. Software algorithms are used to map conventional PLA formats into the new structure. The techniques used provide improved logic function and performance for an FET array technology. Included are descriptions of the PLA architecture and the circuitry that was used.