This paper describes the conceptual design of a highly reliable 108‐Bit Bubble Domain Memory for the Space Program. The Memory has random access to blocks of closed‐loop shift registers, and utilizes self‐contained bubble domain chips with on‐chip decoding. Tradeoff studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit‐per‐chip basis. The final design, has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a “16‐adjacent” code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (≤ 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 μsec to an 800‐word block and an additional 4 msec (average) to a word.