Plasma oxidation techniques described in this issue (1, 2) by the authors were employed alone, or in conjunction with thermal oxidation processes in the fabrication of n‐channel polysilicon gate field effect transistors. Horizontal dimensions were delineated using optical lithography, and ranged from 2.5 μm minimum dimensions up, to enable assessment of device parameters. The characteristics of 500°C plasma oxidized structures were compared to those fabricated in a conventional manner at 1000°C. Gate oxides were 35 nm thick and field planar oxide regions were 350 nm thick. Using wafers of a given resistivity, the thick and thin oxide thresholds of plasma oxide structures were higher than their thermal counterparts due, it is believed, to the absence of surface boron depletion in plasma oxidized regions. In line with this, threshold sensitivity to substrate bias (substrate sensitivity) was greater in plasma oxidized structures for a given starting background substrate doping level. Also because of the absence of impurity spreading, the sheet resistivity of n+ junctions was higher in plasma oxidized structures. Aside from doping level effects which can be advantageously accommodated for by appropriate device design, plasma oxidized devices are otherwise quite comparable to their thermal counterparts. They exhibit obvious device design and process control attributes due to shorter processing time at high temperatures,i.e., absence of oxidation induced stacking faults, confinement of junctions, and absence of surface impurity depletion. In n‐channel devices, the absence of boron depletion during plasma oxidation has enabled the fabrication of surface and junction ion‐implanted devices with lower boron doses and lower substrate sensitivity.