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Memory Latency Effects in Decoupled Architectures with a Single Data Memory Module
Home
Publications
Memory Latency Effects in Decoupled Architectures with a Single Data Memory Module
Memory Latency Effects in Decoupled Architectures with a Single Data Memory Module
LK
L. Kurian
L. Kurian
PH
P.T. Hulina
P.T. Hulina
LC
L.D. Coraor
L.D. Coraor
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25 August 2005
conference paper
Published by
Institute of Electrical and Electronics Engineers (IEEE)
p.
236-245
https://doi.org/10.1109/isca.1992.753320
Abstract
No abstract available
Keywords
DELAY
COMPUTER ARCHITECTURE
CONCURRENT COMPUTING
PERMISSION
HIGH PERFORMANCE COMPUTING
PARALLEL PROCESSING
COMPUTATIONAL MODELING
CLOCKS
INTERLEAVED CODES
COMPUTER SIMULATION
Cited by 3 articles