Programmable DSP architectures. II
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE ASSP Magazine
- Vol. 6 (1), 4-14
- https://doi.org/10.1109/53.16934
Abstract
For pt.I see ibid., vol.5, no.4, p.4-19, Oct. 1988. Three distinct techniques are used for dealing with pipelining, namely, interlocking, time-stationary coding, and data-stationary coding, are examined. These techniques are studied in light of the performance benefit and the impact on the user. Representative DSPs from AT&T, Motorola, and Texas Instruments are used to illustrate the ideas and compare different solutions to the same problems. Trends are discussed, and some predictions for the future are made.Keywords
This publication has 8 references indexed in Scilit:
- A practical C language compiler/optimizer for real-time implementations on a family of floating point DSPsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The application of high-level languages to single-chip digital signal processorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Architectural strategies for an application-specific synchronous multiprocessor environmentIEEE Transactions on Acoustics, Speech, and Signal Processing, 1988
- Pipeline interleaved programmable DSP's: Synchronous data flow programmingIEEE Transactions on Acoustics, Speech, and Signal Processing, 1987
- Pipeline interleaved programmable DSP's: ArchitectureIEEE Transactions on Acoustics, Speech, and Signal Processing, 1987
- Synchronous data flowProceedings of the IEEE, 1987
- Static Scheduling of Synchronous Data Flow Programs for Digital Signal ProcessingIEEE Transactions on Computers, 1987
- An Integrated Automated Layout Generation System for DSP CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985