A 35ns 1Mb CMOS SRAM

1 January 1987

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXX, 258-259
https://doi.org/10.1109/isscc.1987.1157110

Abstract

A 128×8b CMOS SRAM with TTL input/output levels will be presented. The SRAM has been fabricated in a 1.0μm double-poly silicon double-metal CMOS technology Chip size is 8×13.65mm. Typical standby current is 5μA with 100mW dissipatlon at 10MHz. Noise immunity has been achieved from a dual threshold level data transfer.

Keywords

RANDOM ACCESS MEMORY
POWER DISSIPATION
MOS DEVICES
ARTIFICIAL INTELLIGENCE
READ-WRITE MEMORY
YAGI-UDA ANTENNAS
CMOS PROCESS
ELECTRONICS PACKAGING
CIRCUITS

This publication has 2 references indexed in Scilit:

A 30ns 256K full CMOS SRAM
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
A 1Mb virtually SRAM
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1986

Cited by 7 articles