A framework for solving VLSI graph layout problems
- 30 April 1984
- journal article
- Published by Elsevier in Journal of Computer and System Sciences
- Vol. 28 (2), 300-343
- https://doi.org/10.1016/0022-0000(84)90071-0
Abstract
No abstract availableKeywords
This publication has 22 references indexed in Scilit:
- The complexity of minimizing wire lengths in VLSI layoutsInformation Processing Letters, 1987
- Computational aspects of VLSI: J D Ullman, Computer Science Press (1984) 495 ppComputer-Aided Design, 1985
- New lower bound techniques for VLSITheory of Computing Systems, 1984
- Area and Delay Penalties in Restructurable Wafer-Scale ArraysPublished by Springer Nature ,1983
- DPG-Frühjahrstagung in WürzburgPhysikalische Blätter, 1982
- The Compilation of Regular Expressions into Integrated CircuitsJournal of the ACM, 1982
- Minimum Edge Length Planar Embeddings of TreesPublished by Springer Nature ,1981
- A Critique and an Appraisal of VLSI Models of ComputationPublished by Springer Nature ,1981
- An efficient heuristic cluster algorithm for tearing large-scale networksIEEE Transactions on Circuits and Systems, 1977
- P. M. LewisII, R. E. Stearns, and J. Hartmanis. Memory bounds for recognition of context-free and context-sensitive languages. Sixth Annual Symposium on Switching Circuit Theory and Logical Design, University of Michigan, Ann Arbor, Mich., The Institute of Electrical and Electronics Engineers, Inc., New York 1965, pp. 191–202. See Errata, ibid., p. 190.The Journal of Symbolic Logic, 1972