Percolation path and dielectric-breakdown-induced-epitaxy evolution during ultrathin gate dielectric breakdown transient
- 9 September 2003
- journal article
- research article
- Published by AIP Publishing in Applied Physics Letters
- Vol. 83 (11), 2223-2225
- https://doi.org/10.1063/1.1611649
Abstract
A physical model has been developed which complies with the experimental observation on the failure mechanism of ultrathin gate oxide breakdown during constant voltage stress. Dynamic equilibrium needs to be established between the percolation conductive path and the dielectric breakdown induced epitaxy (DBIE) formation during gate dielectric breakdown transient. The model is capable of linking the percolation model, soft breakdown, and hard breakdown to the DBIE growth for a variety of stress conditions and gate oxide thickness without involving new empirical parameters.Keywords
This publication has 8 references indexed in Scilit:
- Breakdown Transients in Ultrathin Gate Oxides: Transition in the Degradation RatePhysical Review Letters, 2003
- Voltage dependence of hard breakdown growth and the reliability implication in thin dielectricsIEEE Electron Device Letters, 2002
- Polarity-dependent dielectric breakdown-induced epitaxy (DBIE) in Si MOSFETsIEEE Electron Device Letters, 2002
- Wear-out, breakdown occurrence and failure detection in 18–25 Å ultrathin oxidesMicroelectronics Reliability, 2001
- Degradation and hard breakdown transient of thin gate oxides in metal–SiO2–Si capacitors: Dependence on oxide thicknessJournal of Applied Physics, 1999
- Non-Gaussian behavior and anticorrelations in ultrathin gate oxides after soft breakdownApplied Physics Letters, 1999
- Model for the current–voltage characteristics of ultrathin gate oxides after soft breakdownJournal of Applied Physics, 1998
- Electrical and thermal transient during dielectric breakdown of thin oxides in metal-SiO2-silicon capacitorsJournal of Applied Physics, 1998