Optimizing VLSI interconnect model for SPICE simulation
- 1 January 1994
- journal article
- research article
- Published by Springer Nature in Analog Integrated Circuits and Signal Processing
- Vol. 5 (1), 87-94
- https://doi.org/10.1007/bf01673909
Abstract
No abstract availableKeywords
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- Challenges and advances in electrical interconnect analysisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- SPICE simulation used to characterize the cross-talk reduction effect of additional tracks grounded with vias on printed circuit boardsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1992
- Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation techniqueIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
- On eddy currents in thin platesElectrical Engineering, 1983