Step-and-repeat projection printing for VLSI circuit fabrication

Abstract

A wafer repeater with 10 × reduction lens for a maximum chip size of 10 mm by 10 mm is described. Calculations of distribution of the light intensity incident on the photoresist are made for a grating and for single lines under different focus and coherence conditions. The wafer repeater was used in fabricating MOS integrated circuits in a double-silicon-gate technology using seven mask levels. Resolution and linewidth control are liable to be degraded by steps appearing on the wafer surface in this technology. An analysis of overlay errors measured near the corners of the chips shows the various error contributions.