A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications
- 1 August 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-33 (8), 737-739
- https://doi.org/10.1109/TC.1984.5009359
Abstract
Error correcting codes are widely used in memory systems to increase reliability. Especially in a memory systern that uses byte-organized memory chips, which each contain b (≫1) output bits, a single chip failure is likely to affect many bits within a byte. Single-bit error correcting-double bit error detecting-single b-bit byte error detecting codes (SEC-DED-SbED codes) are suitable for increasing the reliability of memory system. This correspondence presents a new class of odd-weight-column SEC-DED-SbED codes for b = 4. The code length is 2r-1 - 2[r/2], where r is the number of check bits and [ ] denotes the ceiling or next largest integer. The proposed SEC-DED-S4ED codes are the best-known codes.Keywords
This publication has 7 references indexed in Scilit:
- Error-Correcting Codes with Byte Error-Detection CapabilityIEEE Transactions on Computers, 1983
- Code Constructions for Error Control in Byte Organized Memory SystemsIEEE Transactions on Computers, 1983
- Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory SystemsIEEE Transactions on Computers, 1982
- A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital SystemsIEEE Transactions on Computers, 1978
- Measurement and Generation of Error Correcting Codes for Package FailuresIEEE Transactions on Computers, 1978
- b-Adjacent Error CorrectionIBM Journal of Research and Development, 1970
- A Class of Optimal Minimum Odd-weight-column SEC-DED CodesIBM Journal of Research and Development, 1970