Trends in low-power RAM circuit technologies
- 1 April 1995
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE
- Vol. 83 (4), 524-543
- https://doi.org/10.1109/5.371965
Abstract
No abstract availableThis publication has 44 references indexed in Scilit:
- A 6-ns 4-mb Cmos Sram With Offset-voltage-insensitive Current Sense AmplifiersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- 3-dimensional stacked capacitor cell for 16 M and 64 M DRAMSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Implications of fundamental threshold voltage variations for high-density SRAM and logic circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A charge recycle refresh for Gb-scale DRAM's in file applicationsIEEE Journal of Solid-State Circuits, 1994
- Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI'sIEEE Journal of Solid-State Circuits, 1993
- Sub-1-/spl mu/A dynamic reference voltage generator for battery-operated DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- High-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- A voltage down converter with submicroampere standby current for low-power static RAMsIEEE Journal of Solid-State Circuits, 1992
- A 23-ns 1-Mb BiCMOS DRAMIEEE Journal of Solid-State Circuits, 1990
- A 256K SRAM with on-chip power supply conversionPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987