The physical limitations imposed by geometric effects have been investigated in silicon MOS structures, n-channel silicon gate MOS devices were fabricated using electron-beam lithography and dry-processing techniques. The devices fabricated include discrete transistors, inverters, and ring oscillators. Channel length and width dimensions were independently varied from 10.0 to 0.25 µm. Static short-channel effects were observed and characterized on the discrete transistors and inverters. Dynamic characterization demonstrated stage delays of 65 × 10-12s with a delay-power dissipation figure of merit of 80 × 10-15J. The design, fabrication, and electrical characterization of the devices is described in this paper. The experimental results are shown to be in qualitative agreement with theoretical predictions. The stage delays are shown to be limited by capacitive charging effects (RC delay) and significant performance improvements can be realized with submicrometer geometries. Finally, extrapolations of the data are made in an attempt to determine the ultimate performance limitations expected from the bulk NMOS technology.