An Atm Network Interface for High-Speed Experimentation

Abstract

To connect host computers to an Asynchronous Transfer Mode (ATM) network, a network interface is required. The interface must be able to move data between the network and the host and to convert between the data format used in the network (ATM cells) and that used in the host (eg. variable length protocol data units). In the work described here, the goal was to prototype such an interface and to satisfy two contradictory requirements: speed of operation and flexibility to support experimentation. To achieve this goal, we defined an architecture which uses microprocessors for those functions where most flexibility is required, such as the execution of Segmentation and Reassembly (SAR) algorithms, while more specialized hardware is used for critical high-speed functions such as data movement and formatting of ATM cells. The details of this architecture are described and the results that have been obtained so far with the experimental prototype implementation are presented.