1.2 V mixed analog/digital circuits using 0.3 μm CMOS LSI technology

Abstract

Although dropping the supply voltage below 2 V is effective in reducing power consumption of LSIs for low-power systems, it has not been adopted because it severely degrades the system performance. This paper reports an experimental 1.2 V mixed analog/digital LSI based on 0.3 /spl mu/m laterally-doped buried-layer (LDB) CMOS with /spl plusmn/0.4 V threshold voltages. Based on circuits such as a double feedforward phase-compensated amplifier and a self current cut-off sense amplifier, a 9b 2 MHz 4 mW pipelined A/D converter, a 16 kb 2 mW SRAM with 32 ns access time, and a basic logic gate with a 400 ps delay and 0.4 /spl mu/W/MHz dissipation are realized.<>