Compiler code transformations for superscalar-based high-performance systems
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 11 references indexed in Scilit:
- Instruction-Level Parallel ProcessingScience, 1991
- IMPACTACM SIGARCH Computer Architecture News, 1991
- An instruction-level performance analysis of the Multiflow TRACE 14/300Published by Association for Computing Machinery (ACM) ,1991
- Code compaction for parallel architecturesSoftware: Practice and Experience, 1990
- “Combining” as a compilation technique for VLIW architecturesPublished by Association for Computing Machinery (ACM) ,1989
- Software pipelining: an effective scheduling technique for VLIW machinesPublished by Association for Computing Machinery (ACM) ,1988
- Optimal loop parallelizationPublished by Association for Computing Machinery (ACM) ,1988
- A VLIW architecture for a trace scheduling compilerACM SIGARCH Computer Architecture News, 1987
- Trace Scheduling: A Technique for Global Microcode CompactionIEEE Transactions on Computers, 1981
- Dependence graphs and compiler optimizationsPublished by Association for Computing Machinery (ACM) ,1981