This paper describes the design and testing of a low power Analog to Digital converter. In the design of Z-Plane focal plane array technology the consumption of power by circuitry in the signal processing electronics, that are part of the Z-Plane, is a primary limiting factor in the overall Z-Plane system signal processing architecture. The Analog to Digital converter was designed by applying charge-coupled device (CCD) technology to the binary weighing problem. The Analog to Digital converter is, with the exception of the comparator, an all digital CMOS design. The design concepts are discussed along with preliminary test results.