High-speed graphene transistors with a self-aligned nanowire gate

Abstract

There is considerable interest in graphene for high-speed electronics applications because of its high carrier mobility, but conventional device-fabrication processes produce significant defects in the atomically thin carbon sheets that constitute graphene, severely degrading device performance. Liao et al. report a novel fabrication approach that circumvents such degradation by placing a nanowire, with a metallic core and insulating shell, on top of the graphene as a gate electrode. 'Source' and 'drain' electrodes are then deposited on graphene through a self-alignment process that causes no appreciable damage to the graphene lattice and preserves its high carrier mobility. This unique device layout ensures that the edges of the source, drain and gate electrodes are positioned precisely, enabling a transistor performance that is comparable in speed with the best existing devices of a similar size. There is much interest in graphene for applications in ultrahigh-speed radio-frequency electronics, but conventional device fabrication processes lead to significant defects in graphene. Here a new way of fabricating high-speed graphene transistors is described. A nanowire with a metallic core and insulating shell is placed as the gate electrode on top of graphene, and source and drain electrodes are deposited through a self-alignment process, causing no appreciable damage to the graphene lattice. Graphene has attracted considerable interest as a potential new electronic material1,2,3,4,5,6,7,8,9,10,11. With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics12,13,14,15,16,17,18. However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance19,20,21. Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co2Si–Al2O3 core–shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA μm−1) and transconductance (1.27 mS μm−1) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of fT = 100–300 GHz, with the extrinsic fT (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic fT of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths10.