An Automatic Test Generation System for Illiac IV Logic Boards

1 September 1972

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-21 (9), 1015-1017
https://doi.org/10.1109/tc.1972.5009081

Abstract

A test generation system, developed for the logic boards of the Illiac IV computer, is described. The system combines the test generation by random patterns and the D-algorithm. Some results are given to illustrate the effectiveness of this approach.

Keywords

CIRCUIT FAULTS
COMPUTERS
LOGIC GATES
ADDERS
REDUNDANCY
DATA MINING

This publication has 3 references indexed in Scilit:

Algorithms for Detection of Faults in Logic Circuits
IEEE Transactions on Computers, 1971
The Fastest Computer
Scientific American, 1971
Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits
IEEE Transactions on Electronic Computers, 1967

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