Recent studies have concluded that little parallelism (less than two operations per cycle) is available in sin- gle instruction streams. Since the amount of available parallelism should influence the design of the processor, it is important to verify how much parallelism really ex- ists. In this study we model the execution of the SPEC benchmarks under differing resource constraints. We repeat the work of the previous researchers, and show that under the hardware resource constraints they im- posed, we get similar results. On the other hand, when all constraints are removed except those ~equired by the semantics oft he program, we have found degrees of par- allelism in excess of 17 instructions per cycle. Finally, and perhaps most important for exploiting single in- struction stream parallelism now, we show that if the hardware is properly balanced, one can sustain from 2.0 to 5.8 instructions per cycle on a processor that is rea- sonable to design today.