Prediction and Measurement of Temperature Fields in Silicon-on-Insulator Electronic Circuits

Abstract

Field-effect transistors (FETs) in conventional electronic circuits are in contact with the high-thermal-conductivity substrate. In contrast, FETs in novel silicon-on-insulator (SOI) circuits are separated from the substrate by a thermally resistive silicon-dioxide layer. The layer improves the electrical performance of SOI circuits. But it impedes conduction cooling of transistors and interconnects, degrading circuit reliability. This work develops a technique for measuring the channel temperature of SOI FETs. Data agree well with the predictions of an analytical thermal model. The channel and interconnect temperatures depend strongly on the device and silicon-dioxide layer thicknesses and the channel–interconnect separation. This research facilitates the thermal design of SOI FETs to improve circuit figures of merit, e.g., the median time to failure (MTF) of FET–interconnect contacts.