A newly-developed GaAs static RAM process is described. A large transconductance (gm) of 260 mS/mm has been obtained for enhancement-mode FETs. The large transconductance is accomplished with both buried p-layer SAINT (BP-SAINT) and shallow 30 keV n-layer ion implantation applied to Metallic Amorphous Silicon gate (MAS) FET. A novel static RAM cell layout drastically reduces its cell area to 455 µm2. To realize such a compact cell, tri-level interconnections and electron beam delineated 0.8 µm × 1.3 µm via holes directly on gates and ohmic metals have been developed.