Automating the design of asynchronous sequential logic circuits

Abstract

The computer-aided design process described simplifies the task of designing asynchronous sequential logic circuits (ASLC's). It provides a highly structured, interactive approach for modeling sequential logic functions and for mapping these models into ASLC architectures and gate-level circuits. A design automation system, which implements this process, has been developed and tested. It contains five modules: 1) the behavioral descriptor, which maps the functional design specification into a primitive flow table (PFT); 2) the merger, which minimizes the number of states needed to implement the functional model; 3) the connector, which adds cycles and states, as needed, to avoid critical races; 4) the assigner, which encodes the states and generates the state excitation table and output table; and, finally, 5) the equation generator, which eliminates static hazards and converts the state excitation table and output table into two-level, sum-of-product expressions for the state equations and output equations. This task-oriented system provides a convenient way to describe the functional behavior of sequential logic functions. It can reduce the design cycle time and improve the reliability of the overall ASLC design process and can also be used to facilitate the investigation of alternative ASLC architectures for the purpose of optimizing the performance of a specific sequential logic function.