Adaptation of the P-N Junction Burnout Model to Circuit Analysis Codes

Abstract

Transient electrical pulses impressed upon a circuit containing semiconductors subject the semiconductors to a thermal transient. Potential burnout of the parts is of particular interest and concern. A model is presented which permits the calculation of the transient temperature throughout the semiconductor given the instantaneous power dissipation within the device. The basic technique is to mathematically partition the device by isothermal surfaces, and construct the corresponding RC circuit. Lateral dispersion of the heat (two dimensional heat flow) is included as part of the model. The model has been compared to theory and test. The model is simple and can easily be programmed as a subroutine and attached to existing TREE circuit analysis programs. This permits efficient calculations from the applied electrical pulse to the internal temperature of the semiconductor for prediction of burnout. A demonstration computer solution is shown, and the memory size and run times are given.