An optimized VLSI architecture for a multiformat discrete cosine transform
- 24 March 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 12, 547-550
- https://doi.org/10.1109/icassp.1987.1169851
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- A single chip video rate 16×16 discrete cosine transformPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A two-dimensional fast cosine transformIEEE Transactions on Acoustics, Speech, and Signal Processing, 1985
- A Fast Computational Algorithm for the Discrete Cosine TransformIEEE Transactions on Communications, 1977
- Discrete Cosine TransformIEEE Transactions on Computers, 1974