A fast 16 bit NMOS parallel multiplier
- 1 June 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 19 (3), 338-342
- https://doi.org/10.1109/jssc.1984.1052147
Abstract
An architecture for a fast parallel array multiplier is described. Using a 3 /spl mu/m E/D NMOS process, a 16/spl times/16 bit trial circuit has been designed. A multiplication time of 120 ns has been achieved with a power dissipation of 200 mW and a silicon area of 5 mm/SUP 2/. This architecture concept greatly reduces the logical depth of the array by rearranging internal delays. It is applicable in principle to any MOS, CMOS, GaAs, or bipolar technology.Keywords
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