A neural network implementation of an input access scheme in a high-speed packet switch
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1192-1196
- https://doi.org/10.1109/glocom.1989.64143
Abstract
A neural network implementation of an input access scheme in a high-speed packet switch for broadband ISDN (integrated services digital network) is presented. In this switch, each input maintains a separate queue for each output; thus, in an ( n × n ) switch there will be n 2 input queues. Using synchronous operation, at most one packet per input and output will be transferred at every slot. A neural network maximizing the throughput of this switch is determined, and the form of the energy function, its optimized parameters, and the connection matrix are given. Simulations with random inputs have yielded results close to optimal throughput. This neural network can be implemented with the existing technology for medium switching sizes Author(s) Ali, M.M. Dept. of Electr. Eng., Concordia Univ., Montreal, Que., Canada Nguyen, H.T.Keywords
This publication has 7 references indexed in Scilit:
- Network node interface for new synchronous digital networks-concepts and standardizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Queueing in high-performance packet switchingIEEE Journal on Selected Areas in Communications, 1988
- On the stability of the Travelling Salesman Problem algorithm of Hopfield and TankBiological Cybernetics, 1988
- A Broadband Packet Switch for Integrated TransportIEEE Journal on Selected Areas in Communications, 1987
- “Neural” computation of decisions in optimization problemsBiological Cybernetics, 1985
- Neurons with graded response have collective computational properties like those of two-state neurons.Proceedings of the National Academy of Sciences, 1984
- Neural networks and physical systems with emergent collective computational abilities.Proceedings of the National Academy of Sciences, 1982