Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation

Abstract

A new method is proposed for the fabrication of planar single crystalsiliconnanowires down to 8 nm in diameter. In this method silicon lines are defined on silicon-on-insulator with electron beamlithography followed by a metal liftoff process and a siliconplasmaetch. Low temperature oxidation is then used to shrink these lines to a sub-10 nm diameter. Normal stress generated by the expansion of the viscous oxide during oxidation eventually stops the reaction, leaving a small silicon core at the center of the line. The effect of the crystallographic orientation of the line and the stress complications caused by the substrate are investigated.