Vertical flash memory with protein-mediated assembly of nanocrystal floating gate

Abstract

The authors propose and demonstrate a vertical flash memory device incorporating protein-mediated ordering of nanocrystal floating gate to help circumvent density scaling and/or performance limitations of planar flash memory with continuous floating gate. The scalability of the vertical architecture can allow the theoretical maximum array density of 1 ∕ 4 F 2 ( F : minimum lithographic pitch), thus circumventing the integration density limitations of planar flash transistor arrays. The nanocrystal floating gate renders reasonable retention, while the protein-mediated ordering of nanocrystals allows scalability and manufacturability. With tunneling program/erase, a memory window of 0.5 V , endurance > 10 5 cycles , and retention beyond 10 5 s is reported.