The Prime Memory System for Array Access
- 1 May 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-31 (5), 435-442
- https://doi.org/10.1109/tc.1982.1676020
Abstract
In this paper we describe a memory system designed for parallel array access. The system is based on the use of a prime nwnber of memories and a powerful combination of indexing hardware and data alignment switches. Particular emphasis is placed on the indexing equations and their implementation.Keywords
This publication has 17 references indexed in Scilit:
- The Burroughs Scientific Processor (BSP)IEEE Transactions on Computers, 1982
- Packet Switching Interconnection Networks for Modular SystemsComputer, 1981
- Performance of Processor-Memory Interconnections for MultiprocessorsIEEE Transactions on Computers, 1981
- Interconnection Networks for SIMD MachinesComputer, 1979
- On the Effective Bandwidth of Parallel MemoriesIEEE Transactions on Computers, 1977
- Implementation of Permutation Functions in Illiac IV-Type ComputersIEEE Transactions on Computers, 1976
- Interconnections Between Processors and Memory Modules Using the Shuffle-Exchange NetworkIEEE Transactions on Computers, 1976
- A Shuffle-Exchange Network with Simplified ControlIEEE Transactions on Computers, 1976
- Access and Alignment of Data in an Array ProcessorIEEE Transactions on Computers, 1975
- The Organization and Use of Parallel MemoriesIEEE Transactions on Computers, 1971