Terminal-oriented model for merged transistor logic (MTL)
- 1 October 1974
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 9 (5), 211-217
- https://doi.org/10.1109/jssc.1974.1050505
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Integrated injection logic: a new approach to LSIIEEE Journal of Solid-State Circuits, 1972
- Merged-transistor logic (MTL)-a low-cost bipolar logic conceptIEEE Journal of Solid-State Circuits, 1972
- DC analysis of multiple collector and multiple emitter transistors in integrated structuresIEEE Journal of Solid-State Circuits, 1969
- Transient Analysis and Device Characterization of ACP CircuitsIBM Journal of Research and Development, 1963
- Large-Signal Behavior of Junction TransistorsProceedings of the IRE, 1954