Merged-transistor logic (MTL)-a low-cost bipolar logic concept
- 1 October 1972
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 7 (5), 340-346
- https://doi.org/10.1109/jssc.1972.1052890
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- Super-integrated bipolar memory device for high-density, low-power storagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1971
- A three-mask bipolar integrated circuit structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1969
- Collector diffusion isolated integrated circuitsProceedings of the IEEE, 1969
- Large Scale Integration of MOS Complex Logic: A Layout MethodIEEE Journal of Solid-State Circuits, 1967