Computing optimal clock schedules
- 2 January 2003
- conference paper
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 399-404
- https://doi.org/10.1109/dac.1992.227771
Abstract
Consider the problem of optimizing the parameters of a multiphase clock for a circuit containing both edge-triggered flipflops and level-sensitive latches. We demonstmte that recentJy proposed linear programming approaches to this problem requitw excessive computation time. We give an alternative method in which LP constraints are generated selectively, thus allowing fast solution. Various formulations of short path constraints are discussed, as are experimental results for large circuits.Keywords
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