A two-stage weighted capacitor network for D/A-A/D conversion
- 1 August 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 14 (4), 778-781
- https://doi.org/10.1109/jssc.1979.1051264
Abstract
A two-stage weighted capacitor network for A/D and D/A conversion utilizing a feedback amplifier is described. The two-stage weighted capacitor DAC requires a smaller range of capacitor values then the conventional weighted capacitor DAC and is not subject to the nonlinear effects of parasitic capacitance. Experimental results of such a DAC implemented using a conventional n-channel metal-gate MOS process are presented. A discussion of the comparative accuracy and area of one- and two-stage weighted capacitor DAC's on the basis of capacitor tracking is given.Keywords
This publication has 4 references indexed in Scilit:
- Integrated PCM codecIEEE Journal of Solid-State Circuits, 1979
- MOS sampled data recursive filters using switched capacitor integratorsIEEE Journal of Solid-State Circuits, 1977
- An All-MOS companded PCM voice encoderPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1976
- All-MOS charge redistribution analog-to-digital conversion techniques. IIEEE Journal of Solid-State Circuits, 1975