Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing
- 1 November 1992
- journal article
- Published by Elsevier in Thin Solid Films
- Vol. 220 (1-2), 1-7
- https://doi.org/10.1016/0040-6090(92)90539-n
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Shear mode gridingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Sub-μm, planarized, Nb-AlOx-Nb Josephson process for 125 mm wafers developed in partnership with Si technologyApplied Physics Letters, 1991
- Chemical‐Mechanical Polishing for Fabricating Patterned W Metal Features as Chip InterconnectsJournal of the Electrochemical Society, 1991
- A Two‐Dimensional Process Model for Chemimechanical Polish PlanarizationJournal of the Electrochemical Society, 1991
- Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit InterconnectionsJournal of the Electrochemical Society, 1991
- Chemical processes in glass polishingJournal of Non-Crystalline Solids, 1990
- PSG Flow in High-Pressure SteamJapanese Journal of Applied Physics, 1990
- Novel fabrication technique for dual-gate MOS transistorsMicroelectronic Engineering, 1990
- High-quality thin-film SOI technology using wafer bonding and selective polishing for VLSIsIEEE Transactions on Electron Devices, 1989