Novel fabrication technique for dual-gate MOS transistors
- 1 January 1990
- journal article
- Published by Elsevier in Microelectronic Engineering
- Vol. 10 (2), 115-126
- https://doi.org/10.1016/0167-9317(90)90004-d
Abstract
No abstract availableThis publication has 13 references indexed in Scilit:
- Interface characterization of silicon epitaxial lateral growth over existing SiO/sub 2/ for three-dimensional CMOS structuresIEEE Electron Device Letters, 1989
- The influence of the drain multiplication current on latchup behaviorIEEE Transactions on Electron Devices, 1988
- Hot-electron effects in Silicon-on-insulator n-channel MOSFET'sIEEE Transactions on Electron Devices, 1987
- Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performanceIEEE Electron Device Letters, 1987
- Three-dimensional IC trendsProceedings of the IEEE, 1986
- Analysis of Kink Characteristics in Silicon-on-Insulator MOSFET's Using Two-Carrier ModelingIEEE Journal of Solid-State Circuits, 1985
- Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gateSolid-State Electronics, 1984
- A three-dimensional CMOS design methodologyIEEE Journal of Solid-State Circuits, 1984
- A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layerIEEE Transactions on Electron Devices, 1981
- Autodoping Effects in Silicon EpitaxyJournal of the Electrochemical Society, 1980