A self-aligned gate III-V heterostructure FET process for ultrahigh-speed digital and mixed analog/digital LSI/VLSI circuits
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 36 (10), 2204-2216
- https://doi.org/10.1109/16.40901
Abstract
No abstract availableKeywords
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