PLL design for a 500 MB/s interface

Abstract

When operating pins at high data rates, the key problem is to control timing skews (both on- and off-chip) so data on the pins can be read in a short time. The problem of external skews is solved by a clocking scheme where clock and data signals travel the same distance between the sender and receiver so that there is little skew on the 600-mV/sub pp/ external signals. There are two clocks: one for incoming data (RxClk) and one for outgoing data (TxClk). A PLL (phase-locked loop) generates the properly skewed internal clocks to operate the bus. The PLL consists of one main loop and two fine loops (one each for the receive and transmit clocks). The main loop is a VCO (voltage-controlled oscillator) based second-order loop using a 6-stage, small-swing, differential ring oscillator VCO. It is locked to the incoming RxClk after it is amplified to full CMOS levels. VCO and input clock frequency are halved to allow the phase/frequency detector more time to settle. The fine loop delays the internal clock (relative to the input RxClk) by an amount that causes the sampler to produce high and low outputs with precisely equal frequency, thereby compensating for sampler setup time.<>