A 64 Kbit MOS dynamic random access memory
- 1 April 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 14 (2), 482-485
- https://doi.org/10.1109/jssc.1979.1051200
Abstract
A 65536 word/spl times/1 bit dynamic random access memory is developed using 4 /spl mu/m design rules, a 320-/spl Aring/ thick gate oxide film, and an improved double-poly n-channel silicon gate process. The chip is successfully encapsulated in a standard 16-pin dual-in-line ceramic package, and is able to take over the place that the current 16 Kbit dynamic RAM has occupied. It realizes high speed operation with access time of less than 100 ns and low power dissipation of less than 300 mW.Keywords
This publication has 3 references indexed in Scilit:
- VMOS dynamic RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978
- A-4096 bit one-transistor per-bit RAM with internal timing and low dissipationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1973
- A three transistor-cell, 1024-bit, 500 NS MOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1970