Memory synthesis for high speed DSP applications
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 11.7/1-11.7/4
- https://doi.org/10.1109/cicc.1991.164138
Abstract
Describes technique for performing automatic memory allocation and address allocation for high-speed applications. Memory access conflicts are solved and a global strategy to merge memory units is presented. Efficient reuse of memory locations is obtained by the proposed address allocation techniques. The techniques are based on a stream model for describing data transport. As a specific application, the memory management of the PHIDEO silicon compiler is discussed.Keywords
This publication has 5 references indexed in Scilit:
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